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A20242S - CDCVF2509PWR SMD 3.3-V Phase-Lock Loop Clock Driver (TI)
The CDCVF2509PWR is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509PWR operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509PWR does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2509PWR requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2509PWR is characterized for operation from 0?C to 85?C.
Features:
Spread Spectrum Clock Compatible
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz Is ?125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
25 Ohm On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
Datasheet Available:Texas Instruments CDCVF2509PWR
24-Pin TSSOP package. Manufactured by Texas Instruments.
A20242S
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509PWR does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2509PWR requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2509PWR is characterized for operation from 0?C to 85?C.
Features:
Spread Spectrum Clock Compatible
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz Is ?125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
25 Ohm On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
Datasheet Available:Texas Instruments CDCVF2509PWR
24-Pin TSSOP package. Manufactured by Texas Instruments.
A20242S
$0.70
Original: $1.99
-65%A20242S - CDCVF2509PWR SMD 3.3-V Phase-Lock Loop Clock Driver (TI)—
$1.99
$0.70
Description
The CDCVF2509PWR is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509PWR operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509PWR does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2509PWR requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2509PWR is characterized for operation from 0?C to 85?C.
Features:
Spread Spectrum Clock Compatible
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz Is ?125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
25 Ohm On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
Datasheet Available:Texas Instruments CDCVF2509PWR
24-Pin TSSOP package. Manufactured by Texas Instruments.
A20242S
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCVF2509PWR does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2509PWR requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCVF2509PWR is characterized for operation from 0?C to 85?C.
Features:
Spread Spectrum Clock Compatible
Operating Frequency 50 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz Is ?125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
25 Ohm On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
Datasheet Available:Texas Instruments CDCVF2509PWR
24-Pin TSSOP package. Manufactured by Texas Instruments.
A20242S
