A20280S - SN74AS373DWR SMD Octal D-Type Transparent Latches (TI)
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
Features:
Eight Latches in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
PNP Inputs Reduce DC Loading on Data Lines
Datasheet Available:Texas Instruments SN74AS373DWR
SOIC 20 package.
A20280S

Description
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
Features:
Eight Latches in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
PNP Inputs Reduce DC Loading on Data Lines
Datasheet Available:Texas Instruments SN74AS373DWR
SOIC 20 package.
A20280S











