A20573S - SN74LVC126APWR SMD Quadruple Bus Buffer Gate (TI)

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC126APWR features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

Features:
Operates From 1.65 V to 3.6 V
Specified From ?40?C to 125?C
Inputs Accept Voltages to 5.5 V
Max tpd of 4.7 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C

TSSOP 14 package. Manufactured by Texas Instruments.
A20573S